For an active matrix type liquid crystal display apparatus adopting the dot sequential driving method, when AC driving a liquid crystal panel, each data signal line is pre-charged before a pixel is supplied with a video signal via the data signal line, so that a predetermined amount of charge as desired can be stored in each pixel under stable conditions. In this case, when an attempt is made to pre-charge all the data signal lines at the same time, as the total wiring capacitance of all the data signal lines is large, the power supply of high driving performance is needed. In response, the structure in which the pre-charge is carried out in a unit of some data signal lines has been proposed.
For example, Japanese Laid-Open Patent Application 295520/1995 (Tokukaihei 7-295520/1995, published on Nov. 10, 1995 (corresponding to U.S. Pat. No. 5,686,936 issued on Nov. 11, 1997) hereinafter referred to as patent document 1) discloses the structure wherein when a video signal is supplied to a data signal line, a switch in another data signal line is switched ON with an input of the sampling signal of the video signal outputted from a shift register of the data signal line driver, to pre-charge the data signal line from a pre-charge power supply.
According to the foregoing structure, to dot sequentially output a video signal to each data signal line, a switch with a capacitive control terminal (gate, for example) of a MOSFET including a TFT, etc., is provided in each data signal line. This switch is switched between the conductive state and the non-conductive state by controlling a pre-charge voltage of the control terminal. A control signal (a gate signal, for example) for dot sequentially switching the switch is outputted from the shift register which is generally made up of flip flops of plural stages, after being horizontally shifted by the shift register. Incidentally, in each data signal line, also provided is another switch of the similar structure for pre-charging, which is switched between the conductive state and the non-conductive state.
Further, the foregoing structure of the patent document 1 realizes a smaller area for the pre-charge circuit while ensuring a sufficient frame area of the liquid crystal display apparatus, for example, by storing the pre-charge circuit inside the data signal line driver.
In the data signal line driver of the patent document 1, however, a signal for opening and closing the switch for sampling the video signal is also used as a signal for opening and closing the switch for pre-charging another data signal line, and a problem of deterioration in display quality is therefore liable to occur due to, for example, a less uniform display.
Namely, the pre-charge in the AC driving causes fluctuations in potential of each data signal line and a pixel capacitance, and such fluctuations are large and the polarity of the potential of each data signal line and a pixel capacitance is reversed from that in the previous sampling of the video signal. Therefore, a switching operation of the switch in this state causes a large impulse charging current. Here, as the control terminal of the switch is capacitive, via the capacitance of the control terminal, a relatively high frequency component of such large charging current is transferred to the control signal circuit of the switch via the capacitance of the control terminal, and causes fluctuations in potential of the control signal circuit, thereby causing fluctuations in video signal supplied to the data signal line. Such fluctuations in video signal cause deterioration in display quality, for example, due to a less uniform display.
In response, publication of a US Patent application of the applicant of the present application (No. 2003-0234761 published on Dec. 25, 2003 (hereinafter referred to as patent document 2)) discloses the structure in which an output circuit of a signal for opening/closing the switch for sampling and the output circuit of a signal for opening/closing the switch for pre-charging are not used in common. With this structure, the foregoing problem, i.e., a large current flowing in the data signal line due to the pre-charge causes fluctuations in potential of the video signal to be written in the data signal line, while a write signal is being inputted, via the capacitive control terminal of the pre-charge switch, can be prevented.
In the following, an example structure of the data signal line driver disclosed in the patent document 2 is explained in reference to FIG. 22 and FIG. 23.
As illustrated in FIG. 22, a data signal line driver 131 includes a shift register 131a and a sampling section 131b. This shift register 131a includes set-reset type flip flops srff1, srff2, . . . of plural stages, and also includes switch circuits asw1, asw2, . . . corresponding to respective stages.
These flip flops srff1, srff2, srff3 output output signals dq1, q1, q2, . . . respectively. Then, the output signals q1, q2, . . . from the flip flops srff2 and latter stages are respectively inputted to the switches v_asw1, v_asw2, . . . via buffer Buf1, Buf2, . . . of the sampling section 131b. Each of these switches v_asw1, v_asw2, . . . of the sampling section 131b includes a capacitive control terminal, and conducts with an input of an output signal q1, q2. When the switch is conducted, the potential of an analog video signal VIDEO as inputted in common is outputted to the data signal lines sl1 and sl2, . . . . Namely, the output signals q1, q2, . . . serve as timing pulses for sampling video signals VIDEO.
These output signals dq1, q1 and q2, . . . are sequentially inputted to the switch circuits asw1, asw2, asw3, . . . also as control signals. For these switch circuits asw1, asw2, asw3, . . . , when a switch circuit in the odd-numbered stage is conducted, the switch circuit receives and outputs a clock signal sck. On the other hand, when a switch circuit in the even-numbered stage is conducted, the switch circuit receives and outputs a clock signal sckb. Here, the clock signal sckb is a reversed signal of the clock signal sck.
These switch circuits asw1, asw2, asw3 . . . sequentially output output signals dsr1, sr1, sr2, . . . , and each of these output signals dsr1, sr1, sr2, . . . , serves as a set signal of the flip flop in the next stage and also serves as a reset signal of the flip flop srff in the previous stage. Here, these output signals dsr1, sr1, sr2, . . . are also inputted to the switches p_asw2, p_asw3, . . . of the sampling section 131b. To the flip flop srff1 on the first stage, a start pulse ssp is inputted as a set signal, and this start pulse ssp is also inputted to the switch p_asw1.
As in the case of the switches v_asw1, v_asw2, . . . , each of the switches p_asw1, p_asw2, . . . of the sampling section 131b has a capacitive control terminal, and is conducted with an input of a start pulse ssp, an output signal dsr1, sr1, sr2, . . . . When conducted, the switch outputs a pre-charge potential PVID of a common input signal to the data signal lines sl1, sl2, . . . . Namely, these start pulse ssp, output signals dsR1, sr1, sr2, . . . are control signals for pre-charging.
A plurality of scanning signal lines gl1, gl2, . . . are provided so as to cross the data signal lines sl1, sl2, . . . at right angle. Further, a plurality of pixels Pix1_1, Pix1_2, . . . are provided in a matrix form, respectively at intersections between the data signal lines s1 and the scanning signal lines g1.
FIG. 23 is a timing chart of the data signal line driver 131 of the foregoing structure. In the data signal line driver 131, a start pulse ssp as inputted is also inputted to the switch p_asw1, and the data signal line sl1 is pre-charged. In this state, as the switch v_asw1 is in the non-conductive state, a collision between the pre-charge potential PVID and a potential of the video signal VIDEO on the data signal line sl1 will not occur.
With an input of the start pulse ssp, the output signal dq1 is outputted from the flip flop srff 1, and the switch circuit asw1 is then conducted, and receives a clock signal sck and outputs an output signal dsr1. This output signal dsr1 serves as a set signal of the flip flop srff2, and the flip flop srff2 outputs an output signal q1.
With an input of the output signal q1, the switch asw 2 is conducted, and the switch asw2 receives a clock signal sckb and outputs an output signal sr1. The output signal q1 is inputted to the switch v_asw1 as a timing pulse via the buffer Buf1, and with an input of this output signal q1, the switch v_asw1 is conducted. As a result, the data signal line sl1 is supplied with the video signal VIDEO. In this state, as the start pulse ssp is in the Low level, the switch p_asw1 is set in the non-conductive state. Therefore, in this case also, a collision between the pre-charge potential PVID and a potential of the video signal VIDEO on the data signal line sl1 will not occur.
Incidentally, as the switch p_asw2 is conducted by the output signal dsr1, the video signal VIDEO is outputted to the data signal line sl1, and in the meantime, the data signal line sl2 is pre-charged.
In the foregoing manner, by repetitively carrying out the steps of supplying a video signal VIDEO to the data signal line sln after pre-charging the data signal line sln, and pre-charging a data signal line sl (n+1) while this video signal is being supplied, a dot sequential sampling is performed.
For example, Japanese Laid-Open Patent Application 135093/2001 (Tokukai 2001-135093, published on May 18, 2001 (corresponding to U.S. Pat. No. 6,724,361, issued on Apr. 20, 2004), hereinafter referred to as patent document 3) of the applicant of the present application discloses the structure wherein in response to an output of a set-reset type flip flop in each stage of the shift register, a switch circuit receives a clock signal, and this clock signal is used as a set signal of a set-reset type flip flop in the next stage.
Further, U.S. Pat. No. 6,724,361 issued on Apr. 20, 2004 of the applicant of the present application (hereinafter referred to as patent document 4), and Japanese Laid-Open Patent Application 339985/2000 (Tokukai 2000-339985, published on Dec. 8, 2000, (corresponding to Publication of a US Patent application No. 2003-0174115, published on Sep. 18, 2003) hereinafter referred to as patent document 5) disclose the structure wherein in response to an output of a set-reset type flip flop which constitutes each stage of the shift register, a clock signal is received and the clock signal as received is subjected to the level shifting, and the resulting clock signal as revel shifted is used as a set signal of the set-reset type flip flop in the next stage.
According to the structure of the data signal line driver disclosed in the patent document 2 by the applicant of the present application, a collision between the pre-charge potential PVID and the video signal VIDEO in the data signal line sl is liable to occur, and therefore a video signal potential cannot be written in the data signal line sl under normal conditions, resulting in a deterioration in image quality.
Here, explanations will be given by focusing on the data signal line sl2 in the second line. As illustrated in FIG. 23, an output signal dsr1 for opening and closing the switch p_asw2 for pre-charging the data signal line sl2 and an output signal q2 for opening and closing the switch v_asw2 for sampling the data signal line sl2 are in scyn with respective rise of clock signals sck and sckb which are mutually reversed signals, and it is designed so as to avoid superimposition between these output signals dsr1 and the output signal q2.
In practice, however, as the rise or fall of the pulse is dragged, a superimposition between output signals dsr1 and the output signal q2 may occur partially. Specifically, if the output signal q2 rises before the output signal dsr1 falls, both of the switch p_asw2 for pre-charging and the switch v_asw2 for sampling are set ON at the same time, and a collision between the pre-charge potential PVID and the video signal VIDEO on the data signal line sl2 may occur. Such collision causes fluctuations in video signal sampled to the data signal line sl2, resulting in deterioration in image quality.
The patent document 2 also discloses the structure of the data signal line driver wherein after the fall of a signal for opening/closing the switch for pre-charging, a signal for opening/closing the switch for sampling provided in the same data signal line is raised after the signal is delayed by a half clock cycle. With this structure, a collision between the a pre-charge potential and a video signal on the data signal line can be avoided.
For the display apparatus to be mounted on a portable equipment, etc., it is required to be small in size, and in particular, a frame outside the display area is required to be narrow to realize a compact size display apparatus. However, in order to delay the signal by a half clock cycle, it is required to increase the number of flip flops in the shift register, and which in turn causes an increase in an area of the frame outside the display area. Additionally, in view of the wiring of an output signal in the shift register, although it is demanded to use an output of the flip flop closest to the data signal line, it is not possible to meet such demand with the structure of the patent document 2.
As described, in a driver circuit of a display apparatus such as a conventional data signal line driver, etc., to pre-charge a signal supply line such as a data signal line by the pre-charge circuit stored in the apparatus from a pre-charge power supply of small driving capacity, it is not possible to realize a driver circuit storing a pre-charge circuit of a display apparatus, which can surely prevent a collision between the pre-charge potential and the video signal in a signal supply line when pre-charging the signal supply line from a pre-charge power supply of a small driving performance, while maintaining the number of stages of shift registers to be the required minimum number.
As explained, according to the foregoing conventional driver circuit of a display apparatus, in the case of pre-charging each signal supply line, such as a data signal line from a pre-charge power supply of small driving performance, by means of an internal pre-charge circuit, a collision between a pre-charge potential and a potential of a video signal in a signal supply line cannot be prevented while maintaining the number of stages of shift registers to be the required minimum number. Incidentally, the foregoing patent documents 3 through 5 fail to teach or suggest the pre-charge operation.
For example, Japanese Laid-Open Patent Application 216441/1993 ((Tokukaihei 05-216441/1993 published on Aug. 27, 1993) corresponding to a publication of EP Patent application No. 0,553,832 issued on Aug. 4, 1993; hereinafter referred to as patent document 6) merely discloses the structure which prevents a superimposition between adjacent sampling pulses, and this patent document 6 also does not mention the pre-charge operation.